Semiconductor device fabrication that involves alloying ohmic metal contacts is a technique used for fabricating devices with low contact resistance in the ohmic metal contacts. However, temperatures in excess of 800° C. are typically necessary for alloying ohmic metal contacts for Group III-nitride material devices. However, exposure to such high temperatures creates problems within the channel of the device as well as with the ohmic metal contacts themselves.
Fabrication of low noise devices requires a narrow separation of the source and drain of the transistor. In gallium-nitride (GaN) technology and Group III-nitride technology, achieving a narrow separation between the source and drain becomes difficult due to the high temperature processing step of alloying the source and drain ohmic metal contacts. In general, the ohmic metal contacts have smooth edges, but when exposed to high temperatures, the edges become jagged. In addition, the high temperatures cause the edges of the ohmic metal contacts to move in an uncontrollable manner. These problems place a lower limit on the design of the source-drain separation.
Previously, attempts have been made at fabricating low resistance ohmic metal contacts. In one process, a substrate 5 is provided and a semiconductor layer 10 is deposited on the substrate 5. Next, the source-drain regions are etched in the semiconductor layer 10 using chlorine plasma in a reactive ion etching system. The ohmic metal contacts 20 for the source and drain contact pads, as shown in FIG. 1a, are then deposited on the semiconductor layer 10. The source-drain separation in this procedure is generally about 2 μm. Then, the ohmic metal contacts 20 are annealed for 30 seconds at 875° C. in a nitrogen ambient. This technique helps reduce the resistance of the ohmic metal contacts 20. However, the process does not provide a method for protecting the structure of the ohmic metal contacts 20 from the high temperatures during the annealing process. After the ohmic metal contacts 20 are exposed to the high temperatures, as shown in FIG. 1b, the edges become jagged and the ohmic metal contacts 20 begin to migrate and creep towards one another in an uncontrollable manner. The problem with ohmic metal migration is that it places a lower limit on the design of the device. Typically, the ohmic metal contacts are deposited on the source and drain of a semiconductor device with a desired distance of about 1 micrometer between the source and drain. However, the source and drain may need to be moved further apart to account for the unpredictable migration of the ohmic metal contacts. As a result, it is not always possible to obtain a 1 micrometer separation between the source and drain.
Another problem associated with the high temperatures needed for alloying ohmic metal contacts is that the electron mobility in the channel of transistors is severely reduced when the channel is exposed to high temperatures. Although the physical phenomenon causing the reduction in mobility is unknown, the problem has been experimentally determined. This problem ultimately slows down the speed of the device. In “GaN/AlGaN Heterostructure Field Effect Transistor with Dielectric Recessed Gate,” U.S. Ser. No. 10/214,422 a method for forming a gate recessed into a silicon-nitride (SiN) film is taught. The purpose of this technique is to lower the parasitic resistance of the gate. Using this technique, a substrate 40 is provided and a buffer layer 50 is deposited on the substrate 40. Then, a first and second semiconductor layer 60, 70 are deposited. The first and second semiconductor layers will serve as the channel of the device. The first semiconductor layer 60 is typically GaN, and the second semiconductor layer is typically AlGaN. Finally, a dielectric layer 80, typically SiN, is deposited on the second semiconductor layer 70. A portion of the dielectric layer 80 and second semiconductor layer 70 is removed. Next, ohmic metal contacts 90, as shown in FIG. 2a, are deposited and alloyed at about 875° C. After alloying, the dielectric layer 80 is recessed and a gate 95 is deposited as shown in FIG. 2b. As can be seen in FIGS. 2a and 2b, the ohmic metal contacts for the source and drain are still partly exposed. During subsequent high temperature processing the ohmic metal contacts 90 may creep towards each other. Furthermore, patterning a SiN dielectric layer 80 for gate 95 deposition is extremely difficult and unpractical after the SiN dielectric layer 80 has been exposed to the high alloying temperatures. The technique used to pattern the SiN dielectric layer 80 is likely to cause damage to the second semiconductor layer 70 underneath the gate 95, thereby degrading the performance characteristics of the channel in the semiconductor device.
Therefore, there is a need for a method of fabricating a semiconductor device that can protect the ohmic metal contacts from high temperatures, resulting in the migration of the ohmic metal contacts. There is also a need for a method of fabricating a semiconductor device that can protect the channel and maintain the performance characteristics of the channel in the semiconductor device when the device is exposed to high temperatures.